UPD784938 Datasheet, PDF (346/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
(4) Stopping PPG output
If timer/event counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1) during PPG signal
output, the active level is output irrespective of the output level at the time timer/event counter 2 was stopped.
Figure 11-34. When Timer/Event Counter 2 is Stopped During PPG Signal Output
CR21
CR21
TM2
count value
0H
CR20
CR20
TO2
Caution The output level of the TOn (n = 2, 3) pin when timer output is disabled (ENTOn = 0: n = 2, 3) is the
inverse value of the value set in ALVn (n = 2, 3) bits. Caution is therefore required as the active level
is output when timer output is disabled when the PPG output function has been selected.
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Preliminary User’s Manual U13987EJ1V0UM00