UPD784938 Datasheet, PDF (618/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
24.2.2 Address waits
Address waits are used to secure the address decoding time. If the AW bit of the memory expansion mode register
(MM) is set (to 1), waits are inserted in every memory access^Note. When an address wait is inserted, the high-level period
of the ASTB signal is extended by one system clock cycle (80 ns: fCLK = 12.58 MHz).
Note Except for the internal RAM, internal SFRs, and internal ROM during high-speed fetch.
If it is specified that the internal ROM is accessed in the same cycle as the external ROM, an address wait state
is inserted even when the internal ROM is accessed.
Caution If the pseudo-static RAM refresh function is used when the address wait function is used, the refresh
pulse is output and, at the same time, the memory is accessed. Therefore, do not use the pseudo-static
RAM refresh function when using the address wait function.
Figure 24-10. Address Wait Function Read/Write Timing (1/3)
(a) Read timing with no address wait insertion
fCLK^Note
A8 to A19
High address
Hi-Z
Hi-Z
AD0 to AD7
Low address
Hi-Z
Input data
ASTB
RD
Note fCLK: Internal system clock frequency. This signal is present inside the µPD784938 only.
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Preliminary User’s Manual U13987EJ1V0UM00