UPD784938 Datasheet, PDF (334/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
11.8.3 PWM output
(1) Basic operation of PWM output
In this mode, a PWM signal with the period in which timer counter 2 (TM2) reaches a full count used as one cycle is
output. The timer output (TO2) pulse width is determined by the value of compare register (CR20), and the timer output
(TO3) pulse width is determined by the value of compare register (CR21). When this function is used, the CLR21 bit
and CLR22 bit of capture/compare control register 2 (CRC2) and the CMD2 bit of timer control register 1 (TMC1) must
be set to 0.
The pulse cycle and pulse width are as shown below.
(a) BW2 = 0
• PWM cycle = 256 × x/fXX
• PWM pulse width = CR2n × x/fXXNote; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
Note 0 cannot be set in the CR2n.
PWM pulse width CR2n
• Duty =
=
PWM
256
(b) BW2 = 1
• PWM cycle = 65,536 × x/fXX
• PWM pulse width = CR2n × x/fXXNote; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
Note 0 cannot be set in the CR2n.
• Duty = ^{PWM pulse width} = ^CR2n
PWM cycle
65,536
334
Preliminary User’s Manual U13987EJ1V0UM00