UPD784938 Datasheet, PDF (327/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
TM2
count value
Figure 11-17. TM2 Clearance after Match Detection
FFH
CR20
CR21
CR21
0H
Count start
CE2 ← 1
CLR21 ← 0
Count disabled Count start
CE2 ← 0
CE2 ← 1
CLR21 ← 1
Clear
CR21
Clear
INTC20
interrupt request
INTC21
interrupt request
TO2 pin output
ENTO2 ← 1
ALV2 ← 1
TO3 pin output
ENTO3 ← 1
ALV3 ← 1
OVF2
Inactive level
Inactive level
Cleared by software
Remark CLR22 = 0
11.7.2 Capture operations
Timer/event counter 2 performs capture operations in which the timer counter 2 (TM2) count value is fetched into the
capture register in synchronization with an external trigger, and retained there.
A valid edge detected from the input of the external interrupt request input pins (INTP1/INTP2) is used as the external
trigger (capture trigger). The count value of TM2 in the process of being counted in synchronization with the capture trigger
is fetched into the capture register (CR22) in synchronization with INTP1, or into the capture/compare register (CR21) when
a capture operation is specified in synchronization with INTP2, and is retained there.
The contents of CR21 and CR22 are retained until the next capture triggers corresponding to CR21 and CR22 are
generated.
The capture trigger valid edge is set by means of external interrupt mode register 0 (INTM0). If both rising and falling
edges are set as capture triggers, the width of pulses input from off-chip can be measured, and if a capture trigger is
generated by a single edge, the input pulse cycle can be measured.
See Figure 22-1 for details of the INTM0 format.
When CR21 is used as a capture register, TM2 can be cleared as soon as the contents of TM2 have been captured
by capture trigger to CR21 or CR22.
Preliminary User’s Manual U13987EJ1V0UM00
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