UPD784938 Datasheet, PDF (220/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
(1) Timer counter 0 (TM0)
TM0 is a timer counter that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 0
(PRM0).
The count operation is stopped or enabled by means of timer control register 0 (TMC0).
TM0 can be read only with a 16-bit manipulation instruction. When RESET is input, TM0 is cleared to 0000H and the count
is stopped.
(2) Compare registers (CR00/CR01)
CR00 and CR01 are 16-bit registers that hold the values that determine the interval timer frequency.
If the CR00/CR01 contents match the contents of TM0, an interrupt request (INTC00/INTC01) and timer output control
signal are generated. Also, the count value can be cleared by a content match (CR01).
CR00 and CR01 can be read or written with a 16-bit manipulation instruction. The contents of these registers are undefined
after RESET input.
(3) Capture register (CR02)
CR02 is a 16-bit register that captures the contents of TM0.
The capture operation is synchronized with the input of a valid edge (capture trigger) on the external interrupt request input
pin (INTP3). The contents of the CR02 are retained until the next capture trigger is generated.
CR02 can be read only with a 16-bit manipulation instruction. The contents of this register are undefined after RESET input.
(4) Edge detection circuit
The edge detection circuit detects an external input valid edge.
When the valid edge set by external interrupt mode register 1 (INTM1) is detected in the INTP3 pin input, the external
interrupt request (INTP3), a capture trigger, and a external event count clock are generated (see Figure 22-2 for details
of the INTM1).
(5) Output control circuit
It is possible to invert the timer output when the compare register (CR00, CR01) register contents and the contents of the
timer counter (TM0) match. A square wave can be output from the timer output pins (TO0/TO1) in accordance with the
setting of the low-order 4 bits of the timer output control register (TOC). At this time, PWM output or PPG output can be
performed according to the specification of capture/compare control register 0 (CRC0).
In addition, one-shot pulse output can also be performed by means of a software trigger.
Timer output can be disabled/enabled by means of the TOC. When timer output is disabled, a fixed level is output to the
TO0 and TO1 pins (the output level is set by the TOC).
(6) Prescaler
The prescaler generates the count clock from the internal system clock. The clock generated by this prescaler is selected
by the selector, and is used as the count clock by the timer counter 0 (TM0) to perform count operations.
(7) Selector
The selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as
the count clock of timer counter 0 (TM0).
220
Preliminary User’s Manual U13987EJ1V0UM00