UPD784938 Datasheet, PDF (423/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 16 A/D CONVERTER
16.5 External Circuit of A/D Converter
The A/D converter is provided with a sample & hold circuit to stabilize its conversion operation. This sample & hold circuit
outputs sampling noise during sampling immediately after an A/D conversion channel has been changed.
To absorb this sampling noise, an external capacitor must be connected. If the impedance of the signal source is high,
an error may occur in the conversion result due to the sampling noise. Especially when the scan mode is used, the
impedance of the signal source must be kept low because the channel whose signal is to be converted changes one after
another.
One way to absorb the sampling noise is to increase the capacitance of the capacitor. However, if the capacitance is
increased too much, the sampling noise is accumulated. Therefore, the most effective way is to reduce the resistance
component.
16.6 Cautions
(1) Range of voltages applied to analog input pins
The following must be noted concerning A/D converter analog input pins ANI0 to ANI7 (P70 to P77).
• A voltage outside the range AVSS to AVREF1 should not be applied to pins subject to A/D conversion during an A/D
conversion operation.
If this restriction is not observed, the µPD784938 may be damaged.
(2) Hardware start A/D conversion
Approximately 10 µs is required from the time a valid edge is input to the INTP5 pin until the A/D conversion operation
is actually started. This delay must be taken into account in the design stage. See CHAPTER 22 EDGE DETECTION
FUNCTION for details of the edge detection function.
(3) Connecting capacitor to analog input pins
A capacitor should be connected between the analog input pins (ANI0 to ANI7) and AVSS and between the reference
voltage input pin (AVREF1) and AVSS to prevent misoperation due to noise.
Preliminary User’s Manual U13987EJ1V0UM00
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