UPD784938 Datasheet, PDF (632/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
(b) External memory accesses
When an access is made to an address corresponding to a cleared (to 0) bit in the refresh area specification register
(RFA), a refresh pulse is always output from the REFRQ pin at the same time as the RD signal or WR signal,
irrespective of the cycle specified by the refresh mode register (RFM).
After refresh pulse output, accesses to internal memory or accesses to addresses corresponding to a set (to 1)
bit in the RFA continue, and after the time specified by the RFT0 and RFT1 bits of the RFM has elapsed, a refresh
bus cycle is generated so as not to overlap a memory access cycle, and a refresh pulse is output.
In this way, refreshing can be performed while memory that does not need refreshing, such as PROM, is being
accessed, refresh bus cycle insertions can be reduced, and instruction execution can be performed efficiently.
Figure 24-18. Refresh Pulse Output Operation
ASTB
RD
WR
REFRQ
Read cycle Write cycle Read cycle
Refresh
Read cycle bus cycle Write cycle
Time specified by RFT0 &
RFT1 bits of RFM
In case of access to area in which
memory access operations and refresh
operations are performed exclusively
In case of access to area in which
memory access operations and refresh
operations are performed simultaneously
Time specified by RFT0 & RFT1 bits of
REM.
As refresh pulse has not been output,
refresh bus cycle is inserted
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Preliminary User’s Manual U13987EJ1V0UM00