UPD784938 Datasheet, PDF (339/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
(3) Stopping PWM output
If timer/event counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1) during PWM
signal output, the active level is output.
Figure 11-28. When Timer/Event Counter 2 is Stopped During PWM Signal Output
FFFFH
FFFFH
TM2W
count value
0H
CR20W
CR20W
TO2
Remark ALV2 = 1
Caution The output level of the TOn (n = 2, 3) pin when timer output is disabled (ENTOn = 0: n = 2, 3) is
the inverse of the value set in ALVn (n = 2, 3) bits. Caution is therefore required as the active level
is output when timer output is disabled when the PWM output function has been selected.
Preliminary User’s Manual U13987EJ1V0UM00
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