UPD784938 Datasheet, PDF (515/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 21 CLOCK OUTPUT FUNCTION
21.3.2 1-bit output port
When the CLE bit is cleared (to 0), the contents of the LV bit are output from the CLOCKOUT pin. The CLOCKOUT
pin changes as soon as the contents of the LV bit change.
Figure 21-4. 1-Bit Output Port Operation
LV
CLOCKOUT
21.3.3 Operation in standby mode
SET1 LV instruction executed
CLR1 LV instruction executed
(1) HALT mode
The state prior to setting of the HALT mode is maintained. That is, if, during clock output, clock output has been
performed continuously, and clock output has been disabled, the LV bit contents set before the HALT mode setting
are output unchanged.
(2) STOP mode and IDLE mode
Clock output must be disabled before setting the STOP mode or IDLE mode (this must be done by software). The
CLOCKOUT pin level output is the level before the STOP mode or IDLE mode was set (the contents of the LV bit).
21.4 Cautions
(1) This function cannot be used when the external memory expansion mode is used.
(2) When the external memory expansion mode is used, the clock output mode register (CLOM) should be set to 00H (value
after RESET release).
(3) The other bits (FS0 to FS2 and LV) must not be changed while the CLE bit is set (to 1).
(4) The other bits (FS0 to FS2 and LV) must not be changed at the same time when the CLE bit is changed.
Preliminary User’s Manual U13987EJ1V0UM00
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