UPD784938 Datasheet, PDF (642/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 25 STANDBY FUNCTION
25.3 HALT Mode
25.3.1 HALT mode setting and operating status
The HALT mode is selected by setting (to 1) the HLT bit of the standby control (STBC) register.
The only writes that can be performed on STBC are 8-bit data writes by means of a dedicated instruction. HALT mode
setting is therefore performed by means of the “MOV STBC, #byte” instruction.
Caution If HALT mode setting is performed when a condition that releases HALT mode is in effect, HALT mode
is not entered, and execution of the next instruction, or a branch to a vectored interrupt service
program, is performed. To ensure that a definite HALT mode setting is made, interrupt requests should
be cleared (to 0), etc. before entering HALT mode.
Table 25-1. Operating Status in HALT Mode
Clock oscillator
Internal system clock
CPU
I/O lines
Peripheral functions
Internal RAM
Bus lines
RD, WR output
ASTB output
REFRQ output
HLDRQ input
HLDAK output
AD0 to AD7
A8 to A19
Operating
Operating
Operation stopped^Note
Retain status prior to HALT mode setting
Continue operating
Retained
High-impedance
Retained
High level
Low level
Continue operating
Continue operating (input)
Continue operating
Note Macro service processing is executed.
25.3.2 HALT mode release
HALT mode can be released by the following three sources.
• Non-maskable interrupt request
• Maskable interrupt request (vectored interrupt/context switching/macro service)
• RESET input
Release sources and an outline of operations after release are shown in Table 25-2.
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Preliminary User’s Manual U13987EJ1V0UM00