UPD784938 Datasheet, PDF (446/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
18.3.4 Operation when transmission only is enabled
A transmit operation is performed when the CTXE1 bit of clocked serial interface mode register (CSIM1) is set (to 1).
The transmit operation starts when a write to the serial shift register (SIO1) is performed while the CTXE1 bit is set (to 1).
When the CTXE1 bit is cleared (to 0), the SO1 pin is in the output high level.
(1) When the internal clock is selected as the serial clock
When transmission starts, the serial clock is output from the SCK1 pin and data is output in sequence from SIO1 to
the SO1 pin in synchronization with the fall of the serial clock, and SI1 pin signals are shifted into SIO1 in synchronization
with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1.
If transmission is disabled during the transmit operation (by clearing (to 0) the CTXE1 bit), SCK1 clock output is stopped
and the transmit operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is
not generated, and the SO1 pin becomes output high level.
(2) When an external clock is selected as the serial clock
When transmission starts, data is output in sequence from SIO1 to the SO1 pin in synchronization with the fall of the
serial clock input to the SCK1 pin after the start of transmission, and SI1 pin signals are shifted into SIO1 in
synchronization with the rise of the SCK1 pin input. If transmission has not started, shift operations are not performed
and the SO1 pin output level does not change even if the serial clock is input to the SCK1 pin.
If transmission is disabled during the transmit operation (by clearing (to 0) the CTXE1 bit), the transmit operation is
discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated, and
the SO1 pin becomes output high level.
18.3.5 Operation when reception only is enabled
A receive operation is performed when the CRXE1 bit of the clocked serial interface mode register (CSIM1) is set (to
1). The receive operation starts when the CRXE1 changes from “0” to “1”, or when a read from serial shift register (SIO1)
is performed.
(1) When the internal clock is selected as the serial clock
When reception starts, the serial clock is output from the SCK1 pin and the SI1 pin data is fetched in sequence into
serial shift register (SIO1) in synchronization with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of reception and the first fall of SCK1.
If reception is disabled during the receive operation (by clearing (to 0) the CRXE1 bit), SCK1 clock output is stopped
and the receive operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is not
generated, and the contents of the SIO1 are undefined.
(2) When an external clock is selected as the serial clock
When reception starts, the SI1 pin data is fetched into serial shift register (SIO1) in synchronization with the rise of
the serial clock input to the SCK1 pin after the start of reception. If reception has not started, shift operations are not
performed even if the serial clock is input to the SCK1 pin.
If reception is disabled during the receive operation (by clearing (to 0) the CRXE1 bit), the receive operation is
discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated.
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Preliminary User’s Manual U13987EJ1V0UM00