UPD784938 Datasheet, PDF (541/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
23.3.4 Interrupt mode control register (IMC)
IMC contains the PRSL flag. The PRSL flag specifies enabling/disabling of nesting of maskable interrupts for which
the lowest priority level (level 3) is specified.
When IMC is manipulated, the interrupt disabled state (DI state) should be set first to prevent misoperation.
IMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
RESET input sets IMC to 80H.
Figure 23-4. Interrupt Mode Control Register (IMC) Format
7
6
5
4
3
2
1
0 Address After reset R/W
IMC PRSL 0
0
0
0
0
0
0 0FFAAH
80H
R/W
PRSL
Control of Nesting Operations for
Maskable Interrupts (Lowest Level)
0 Nesting between interrupts set as level 3
(lowest level) enabled
1 Nesting between interrupts set as level 3
(lowest level) disabled
Preliminary User’s Manual U13987EJ1V0UM00
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