UPD784938 Datasheet, PDF (380/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 12 TIMER 3
12.4.2 Clear operation
(1) Clear operation by match with compare register (CR30)
Timer counter 3 (TM3) is cleared automatically after a match with the compare register (CR30). When a clearance
source arises, TM3 is cleared to 0H on the next count clock. Therefore, even if a clearance source arises, the value
at the point at which the clearance source arose is retained until the next count clock arrives.
Figure 12-6. TM3 Clearance by Match with Compare Register (CR30)
Count clock
TM3
n-1
n
0
1
Compare register
(CR30)
n
TM3 and CR30 match Cleared here
(2) Clear operation by CE3 bit of timer control register 0 (TMC0)
TM3 is also cleared when the CE3 bit of TMC0 is cleared (to 0) by software. The clear operation is performed following
clearance (to 0) of the CE3 bit in the same way.
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Preliminary User’s Manual U13987EJ1V0UM00