UPD784938 Datasheet, PDF (269/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
(4) While an instruction that writes data to the compare register (CR0n: n = 0, 1) is executed, coincidence between CR0n, to
which the data is to be written, and timer counter 0 (TM0) is not detected. For example, if the contents of CR0n do not change
before and after the writing, the interrupt request is not generated even if the value of TM0 coincides with the value of CR0n,
nor does the timer output (TOn: n = 0, 1) change.
Write data to CR0n when timer/event counter 0 is executing counting operation, in the timing that the contents of TM0 do
not coincide with the value of CR0n before and after writing (e.g., immediately after an interrupt request has been generated
because TM0 and CR0n have coincided).
(5) Coincidence between TM0 and compare register (CR0n: n = 0, 1) is detected only when TM0 is incremented. Therefore,
the interrupt request is not generated even if the same value as TM0 is written to CR0n, and the timer output (TOn: n = 0,
1) does not change.
(6) If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the CR0n
cannot be rewritten by interrupt processing that is performed on coincidence between TM0 and the compare register (CR0n:
n = 0, 1). Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked).
(7) The output level of the TOn (n = 0, 1) when the timer output is disabled (ENTOn = 0: n = 0, 1) is the reverse value of the
value set to the ALVn (n = 0, 1) bit. Note, therefore, that an active level is output when the timer output is disabled with the
PWM output function or PPG output function selected.
(8) When timer/event counter 0 is used as an external event counter, it is not possible to distinguish between the case where
there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 0 (TM0)
alone (refer to Figure 9-53), since the contents of TM0 are 0 in both cases. If it is necessary to make this distinction, the
INTP3 interrupt request flag should be used. To make a distinction, use the interrupt request flag of INTP3, as shown in
Figure 9-54.
Figure 9-53. Example of the Case where the External Event Counter does Not Distinguish
between One Valid Edge Input and No Valid Edge Input
INTP3
TM0 0
0
Cannot be
distinguished
Count start
1
2
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