UPD784938 Datasheet, PDF (633/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
(2) Self-refresh operation
This mode is used to retain the contents of pseudo-static RAM in standby mode.
(a) Self-refresh operation mode setting
When bit 4 (RFEN) of the refresh mode (RFM) register is set to “1”, and bit 7 (RFLV) to “0”, a low level is output
from the REFRQ pin, and the self-refresh operation mode is specified for the pseudo-static RAM.
(b) Return from self-refresh operation
Refresh pulse output to the pseudo-static RAM is disabled approximately 200 ns^Note after the REFRQ pin output
level changes from low to high. Therefore, the µPD784938 arranges for refresh pulses not to be output during
the disabled time by raising the REFRQ pin in synchronization with the refresh timing counter.
To enable this low-to-high transition of the REFRQ pin level to be recognized, the RFLV bit read level is set (to
1) when the REFRQ pin level changes from low to high.
Note This time varies according to the speed rank, etc. of the pseudo-static RAM.
Figure 24-19. Timing for Return from Self-Refresh Operation
Self refresh mode Approximately min. 200 ns^Note
REFRQ
Refresh timing
counter output
RFLV bit
Note Refreshing disabled time
Software set operation execution
Preliminary User’s Manual U13987EJ1V0UM00
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