UPD784938 Datasheet, PDF (645/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 25 STANDBY FUNCTION
Table 25-3. HALT Mode Release by Maskable Interrupt Request
Release Source MK^{Note 1} IE^{Note 2}
State on Release
Operation after Release
Maskable
0
interrupt request
(excluding macro
service request)
1
• Interrupt service program not being
Interrupt request acknowledgment
executed
• Low-priority maskable interrupt service
program being executed
• PRSL bit^{Note 4} cleared (to 0) during execution
of priority level 3 interrupt service program
• Same-priority maskable interrupt service
program being executed
(If PRSL bit^{Note 4} is cleared (to 0), excluding
execution of priority level 3 interrupt
service program)
• High-priority interrupt service program
being executed
Execution of instruction after MOV STBC,
#byte instruction (interrupt request that
released HALT mode is held pending^{Note 3})
0
0
—
1
×
—
HALT mode maintained
Macro service
request
0
×
—
Macro service processing execution
End condition not established → HALT
mode again
End condition established
→ If VCIE^{Note 5} = 1: HALT mode again
If VCIE^{Note 5} = 0: Same as release
by maskable interrupt request
1
×
—
HALT mode maintained
Notes 1. Interrupt mask bit in individual interrupt request source
2. Interrupt enable flag in program status word (PSW)
3. Pending interrupt requests are acknowledged when acknowledgment becomes possible.
4. Bit in interrupt mode control register (IMC)
5. Bit in macro service mode register of macro service control word in individual macro service request source
(3) Release by RESET input
The program is executed after branching to the reset vector address, as in a normal reset operation. However, internal
RAM contents retain their value directly before HALT mode was set.
Preliminary User’s Manual U13987EJ1V0UM00
645