UPD784938 Datasheet, PDF (491/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
(7) Data register (DR)
[During transmission unit]
The data (1 byte) written to the data register (DR) is stored to the internal shift register of the IEBus. It is then output
from the most significant bit, and an interrupt (INTIE1) is issued to the CPU each time 1 byte has been transmitted.
INTIE is generated at the timing of the data register (DR) value stored in the internal shift register of the IEBus.
However, INTIE1 is not generated when the last byte and the 32nd byte (last byte of one communication frame)
is delivered to the internal register.
[During reception unit]
One byte of the data received by the internal shift register of the IEBus is stored to this register.
Each time 1 byte has been correctly received, an interrupt (INTIE1) is issued.
Figure 20-21. Data Register (DR) Format
7
6
5
4
3
2
1
0 Address After reset R/W
DR
0FFBAH 00H R/W
Sets communication data (8 bits)
Caution If the next data is not in time while the transmission unit is set, an underrun occurs, and a
communication error interrupt (INTIE2) occurs.
An instruction of Read Modify Write mode (such as XCH and ROL4) cannot be used for DR.
Preliminary User’s Manual U13987EJ1V0UM00
491