UPD784938 Datasheet, PDF (447/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
18.3.6 Operation when transmission/reception is enabled
When the CTXE1 bit and CRXE1 bit of the clocked serial interface mode register (CSIM1) register are both set (1), a
transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/
receive operation is started when the CRXE1 bit is changed from “0” to “1”, or by performing a write to serial shift register
(SIO1).
When a transmit/receive operation is started for the first time, the CRXE1 bit always changes from “0” to “1”, and there
is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. The first
transmit data should therefore be written to SIO1 beforehand when both transmission and reception are disabled (when
the CTXE1 bit and CRXE1 bit are both cleared (to 0)), before enabling transmission/reception. However, specify whether
data is transferred with MSB or LSB first before writing the SIO1. Even if the specification is made after writing the SIO1,
the byte order of the data already stored in the SIO1 cannot be changed.
When transmission/reception is disabled (CTXE1 = CRXE1 = 0), the SO1 pin is in the output high level.
(1) When the internal clock is selected as the serial clock
When transmission/reception starts, the serial clock is output from the SCK1 pin, data is output in sequence from serial
shift register (SIO1) to the (SO1) pin in synchronization with the fall of the serial clock, and SI1 pin data is shifted in
order into SIO1 in synchronization with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,
the contents of the SIO1 will be undefined.
If transmission and reception are disabled simultaneously, SCK1 clock output is stopped and the transmit and receive
operations are discontinued on the next rise of SCK1. When transmission and reception are disabled simultaneously,
the contents of SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output
high level.
(2) When an external clock is selected as the serial clock
When transmission/reception starts, data is output in sequence from serial shift register (SIO1) to the SO1 pin in
synchronization with the fall of the serial clock input to the SCK1 pin after the start of transmission/reception, and SI1
pin data is shifted in order into SIO1 in synchronization with the rise of the serial clock. If transmission/reception has
not started, the SIO1 shift operations are not performed and the SO1 pin output level does not change even if the serial
clock is input to the SCK1 pin.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,
the contents of the SIO1 will be undefined.
If transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and
subsequent SCK1 input is ignored. When transmission and reception are disabled simultaneously, the contents of
SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level.
18.3.7 Corrective action in case of slippage of serial clock and shift operations
When an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and
shift operations due to noise, etc. In this case, since the serial clock counter is initialized by disabling both transmit operations
and receive operations (by clearing (to 0) the CTXE1 bit and CRXE1 bit), synchronization of the shift operations and the
serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first
clock.
Preliminary User’s Manual U13987EJ1V0UM00
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