UPD784938 Datasheet, PDF (634/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
24.4 Bus Hold Function
The bus hold function is provided for the connection of a device that functions as the bus master, such as a DMA controller.
In response to a request from the bus master device, all local bus interface pins are set to high impedance (except HLDAK),
and local bus interface mastership is passed to that device.
The bus hold function cannot be used when the external wait function or refresh function is used.
24.4.1 Hold mode register (HLDM)
HLDM is an 8-bit register that specifies enabling/disabling of the bus hold function. HLDM format is shown in Figure
24-20.
When RESET is input, HLDM is cleared to 00H, so that the bus hold function is disabled. The HLDRQ and HLDAK pins
are set to port mode and operate as the P66 and P67 pins.
Figure 24-20. Hold Mode Register (HLDM) Format
7
6
5
4
3
2
1
0 Address After reset R/W
HLDM HLDE 0
0
0
0
0
0
0 0FFC5H 00H
R/W
HLDE Bus Hold Enabling/Disabling P66
P67
0 Disabled
Port
1 Enabled
HLDRQ HLDAK
Caution The bus hold function must be disabled when the external wait function or refresh function is used.
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Preliminary User’s Manual U13987EJ1V0UM00