UPD784938 Datasheet, PDF (394/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 14 WATCH TIMER
The watch timer of the µPD784938 does not have a buzzer output function.
Table 14-1. Relation between Count Clock and Watch Timer Operation
Count Clock Selection
Main clock
Watch clock
Normal Operation Mode
Operable
Operable
HALT mode
Operable
Operable
Type of Standby Mode
STOP mode
Stopped
Operable
IDLE mode
Operable^Note
Operable
Note When bit 3 (WM3) of the watch timer mode register (WM) is set to “1” and bit 6 (WM6) of the same register is
set to “0”, main clock operation in the IDLE mode is enabled.
The watch timer consists of a divider circuit that divides the count clock by three, and a counter that divides the output
signal of the divider circuit by 2¹⁴. As the count clock, select the signal obtained by dividing the internal system clock by
128, or the signal from the watch clock oscillator.
Figure 14-2. Block Diagram of Watch Timer
WM.3
reset
Main clock
fXX/128
1/3
divider
Watch
clock
oscillator
0
SEL
1
ON/OFF
12 34 5
6 78 9
Counter
Counter
0S
E
L
WM.4
0
SEL
1
WM.2
10 11 12 13
Counter
14
1
SEL
0
INTW
WM.7
WM.6
STBC.7
(Set by instruction when main clock is 12.58 MHz)
Caution The interval until the first INTW is generated is not 0.5 second after the operation has been enabled.
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Preliminary User’s Manual U13987EJ1V0UM00