UPD784938 Datasheet, PDF (506/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
20.6.4 Slave reception
Start
<1>
Broad-
casting
M address P S address P A
Approx. 1,014 µ s (mode 1)
Control
PA
Telegraph
length
PA
Data 1
Data 1
Approx. 390 µ s
(mode 1)
6
6
P A Data 2 P A
Data n–1
6
PA
Data n
6<2>
PA
n = Final number of data bytes
Initial preparation processing
Sets a unit address.
Communication start processing
Sets the bus control register (enables communication, disables slave transmission, and enables slave reception).
<1> Interrupt (INTIE2) occurrence
Judgment of occurrence of error
↓
Judgment of slave request
→ Error processing
→ Slave processing^{Note 1}
Interrupt (INTIE1) occurrence^{Note 1}
The receive data stored to the data register (DR) is read by macro service.
At this time, the data transfer direction is SFR (peripheral) → RAM (memory).
<2> Interrupt (INTIE2) occurrence
Judgment of occurrence of error →
↓
Judgment of end of communication →
↓
Judgment of end of frame
→
Error processing
End of communication processing
End of frame processing^{Note 2}
Notes 1. If NACK is transmitted in the data field, an interrupt (INTIE1) is not issued to the CPU, but the same
data is retransmitted from the master.
If the receive data is not read in time until the next data is received, NACK is automatically transmitted.
2. The vector interrupt processing in <2> judges whether the data has been correctly received within one
frame.
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Preliminary User’s Manual U13987EJ1V0UM00