UPD784938 Datasheet, PDF (489/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
In the case of <4> and <5>, communication is performed from other than lock request in the locked status, so that
even if the unit address is the target of the communication, no start interrupt or communication end interrupt (INTIE2)
is generated. However, if a slave status, lock address request is received, the status transmission flag (bit 4 of
interrupt status register (ISR)) is set, and a status interrupt request (INTIE2) is generated. In this way, even if the
same control data is received in the locked status, the INTIE2 generation timing differs depending on whether the
master side is the lock request address (<3>) or it is a different address.
Figure 20-18. INTIE2 Interrupt Generation Timing in Locked Status (in case of <4>, <5>)
IEBus
sequence
Start
Broad-
casting
<Control field>
Master address
(12 + A)
Slave address
(12 + P + A)
Control
Telegraph
length
Data
(4 + P + A) _{(8 + P + A)} (8 + P + A)
INTIE2
Status interrupt
Figure 20-19. INTIE2 Interrupt Generation Timing in Locked Status (in case of <3>)
IEBus
sequence
Start
Broad-
casting
<Control field>
Master address
(12 + P)
Slave address
(12 + P + A)
Telegraph
Control _length
Data
(4 + P + A) _{(8 + P + A)} (8 + P + A)
INTIE2
Start interrupt
Status Communication
interrupt end interrupt
Preliminary User’s Manual U13987EJ1V0UM00
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