UPD784938 Datasheet, PDF (488/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
[Slave status response operation]
The ACK response operation of the control field differs depending on the status of slave side when a slave status
request (control data: “0H, 6H”) and a lock address request “4H, 5H” are received.
<1> In unlocked status, when “0H, 6H” control data is received →
<2> In unlocked status, when “4H, 5H” control data is received →
<3> In locked status, when “0H, 4H, 5H, 6H” control data is
→
received from the request unit
<4> In locked status, when “0H, 4H, 5H” control data is received
from an address other than the request unit
→
<5> In locked status, when “6H” control data is received from an
address other than the request unit
→
Return ACK
Don’t return ACK
Return ACK
Return ACK
Return ACK
In all cases from <1> to <5>, the status transmission flag (bit 4 of the interrupt status register (ISR)) is set upon
reception of the slave status and lock address request, and the status interrupt request (INTIE2) is generated. The
generation timing is the end of the control field parity bit (start of the ACK bit).
However, if ACK communication is not performed, an NACK error occurs at the end of the ACK bit and communication
is stopped.
Figure 20-16. Interrupt Generation Timing (in case of <1>, <3>, <4>)
IEBus
sequence
Control bits (4 bits)
<Control field>
Parity bit (1 bit)
ACK bit (1 bit)
End with communication error
INTIE2
Status
transmission flag
Internal
NACK flag
IEBus
sequence
Flag is set upon reception
of “0H, 4H, 5H, 6H”
Flag is reset with CPU processing
Figure 20-17. Interrupt Generation Timing (in case of <2>, <5>)
Control bits (4 bits)
<Control field>
Parity bit (1 bit)
ACK bit (1 bit)
End with communication error
INTIE2
Status
transmission flag
Internal
NACK flag
Flag is reset with
Flag is set upon reception ^{CPU processing}
of “0H, 4H, 5H, 6H”
Error is set upon
NACK detection
488
Preliminary User’s Manual U13987EJ1V0UM00