UPD784938 Datasheet, PDF (240/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.7.3 PWM output
(1) Basic operation of PWM output
In this mode, a PWM signal with the period in which timer counter 0 (TM0) reaches a full count used as one cycle is output.
The timer output (TO0) pulse width is determined by the value of compare register (CR00), and the timer output (TO1) pulse
width is determined by the value of compare register (CR01). When this function is used, the CLR01 bit of capture/compare
control register 0 (CRC0) must be set to 0.
The pulse cycle and pulse width are as shown below.
• PWM cycle = 65,536 × x/fXX
• PWM pulse width = CR0n × x/fXX^Note; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
Note 0 cannot be set in the CR0n.
• Duty = ^{PWM pulse width} = ^CR0n
PWM cycle
65,536
Remark n = 0, 1
Figure 9-17. PWM Pulse Output
Timer count
Count start
0H
CR00
Interrupt
TO0
FFFFH
CR00
FFFFH
FFFFH
CR00
Pulse
width
Pulse cycle
Pulse width
Pulse cycle
Remark ALV0 = 0
Table 9-7. TO0, TO1 PWM Cycle (fXX = 12.58 MHz)
Count Clock
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
fXX/256
fXX/512
fXX/1,024
Minimum Pulse Width [µs]
0.32
0.64
1.27
2.54
5.09
10.17
20.35
40.70
81.40
PWM Cycle [s]
0.02
0.04
0.08
0.17
0.33
0.67
1.33
2.67
5.33
PWM Frequency [Hz]
47.6
23.8
12.0
6.0
3.0
1.5
0.7
0.4
0.2
240
Preliminary User’s Manual U13987EJ1V0UM00