UPD784938 Datasheet, PDF (588/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
Figure 23-35. Automatic Addition Control + Ring Control Block Diagram 1
(when output timing varies with 1-2-phase excitation)
1 M memory space
Macro service control word,
macro service channel
(internal RAM)
1237FEH ^{∆ t512}
...
∆ t2
Output timing: 123400H ∆t1
123007H
D7
...
Output data (8 items)
D1
123000H
D0
MSC
0FE5AH
TSFRP
02H
–1
00H
14H Low-order 8 bits of CR10 address
12H
MPT
34H
+2
00H
DSFRP 0EH Low-order 8 bits of P0L address
12H
MPD
30H
+1
00H
MR
08H
RC
08H
–1
Addition
Channel
pointer
Mode
register
5AH
7FH Type C, MPT/MPD incremented,
2-byte timer data, automatic addition,
ring control, interrupt request
generation at MSC = 0
Compare register
CR10W
Match
Timer counter 1
TM1W
Buffer register
P0L
INTC10
Output
latch P0
P00
P01 _{To stepping}
P02 ^motor
P03
Remark Internal RAM addresses in the figure are the values when the LOCATION 0 instruction is executed.
When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values in the figure.
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Preliminary User’s Manual U13987EJ1V0UM00