UPD784938 Datasheet, PDF (221/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.3 Timer/Event Counter 0 Control Registers
(1) Timer control register 0 (TMC0)
The timer/event counter 0 TM0 count operation is controlled by the low-order 4 bits in the TMC0 (the high-order 4 bits control
the count operation of the TM3/TM3W of the timer 3).
TMC0 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of TMC0
is shown in Figure 9-2.
RESET input clears TMC0 to 00H.
Figure 9-2. Timer Control Register 0 (TMC0) Format
7
6
TMC0 CE3 0
5
4
3
2
1
0 BW3 CE0 OVF0 0
0 Address After reset R/W
0 0FF5DH
00H
R/W
Remark The OVF0 bit is reset by software only.
OVF0
TM0 Overflow Flag
0 No overflow
1 Overflow (count up from FFFFH to 0000H)
CE0
TM0 Count Operation Control
0 Count operation stopped with count
cleared
1 Count operation enabled
Countrols count operation of the TM3/TM3W of the
timer 3 (see Figure 12-2).
Preliminary User’s Manual U13987EJ1V0UM00
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