UPD784938 Datasheet, PDF (528/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
Remarks 1. The default priority is a fixed number. This indicates the order of priority when interrupt requests specified
as having the same priority are generated simultaneously,
2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used
simultaneously). Therefore, although the same hardware is used for the interrupts, two names are
provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2.
23.1.1 Software interrupts
Interrupts by software consist of the BRK instruction which generates a vectored interrupt and the BRKCS instruction
which performs context switching.
Software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control.
23.1.2 Operand error interrupts
These interrupts are generated if there is an illegal operand in an MOV STBC, #byte instruction or MOV WDMC, #byte
instruction, and LOCATION instruction.
Operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control.
23.1.3 Non-maskable interrupts
A non-maskable interrupt is generated by NMI pin input or the watchdog timer.
Non-maskable interrupts are acknowledged unconditionally^Note, even in the interrupt disabled state. They are not subject
to interrupt priority control, and are of higher priority that any other interrupt.
Note Except during execution of the service program for the same non-maskable interrupt, and during execution of the
service program for a higher-priority non-maskable interrupt
23.1.4 Maskable interrupts
A maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. In addition,
acknowledgment enabling/disabling can be specified for all maskable interrupts by means of the IE flag in the program status
word (PSW).
In addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro
service (though some interrupts cannot use macro service: see Table 23-2).
The priority order for maskable interrupt requests when interrupt requests of the same priority are generated
simultaneously is predetermined (default priority) as shown in Table 23-2. Also, multiprocessing control can be performed
with interrupt priorities divided into 4 levels. However, macro service requests are acknowledged without regard to priority
control or the IE flag.
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Preliminary User’s Manual U13987EJ1V0UM00