UPD784938 Datasheet, PDF (231/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
The TM0 count operation is controlled by the CE0 bit of the timer control register 0 (TMC0) in the same way as with basic
operation.
When the CE0 bit is set (to 1) by software, the contents of TM0 are set to 0000H and the count-up is started on the initial count
clock.
When the CE0 bit is cleared (to 0) by software during a TM0 count operation, the contents of TM0 are set to 0000H immediately
and the stopped state is entered. The TM0 count operation is not affected if the CE0 bit is set (to 1) by software again when
it is already set (to 1).
Caution When timer/event counter 0 is used as an external event counter, it is not possible to distinguish between
the case where there is no valid edge input at all and the case where there is a single valid edge input, using
the timer counter 0 (TM0) alone (see Figure 9-11), since the contents of TM0 are 0 in both cases. If it is
necessary to make this distinction, the INTP3 interrupt request flag should be used. An example is shown
in Figure 9-12.
Figure 9-11. Example of the Case where the External Event Counter does Not Distinguish between One
Valid Edge Input and No Valid Edge Input
INTP3
TM0 0
0
1
2
No distinction made
Count start
Preliminary User’s Manual U13987EJ1V0UM00
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