UPD784938 Datasheet, PDF (285/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 10 TIMER/EVENT COUNTER 1
10.5 External Event Counter Function
Timer/event counter 1 can count clock pulses input from the external interrupt request input pin (INTP0) pin.
No special selection method is needed for the external event counter operation mode. When the timer counter 1 (TM1) count
clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 1 (PRM1), TM1 operates
as an external event counter.
The maximum frequency of the external clock pulse that can be counted by the external event counter is determined by the
sampling clock select register (SCS0) as shown in Table 10-4.
The maximum frequency is the same when both the edges of the INTP0 input are counted and when only one edge is counted.
The pulse width of the INTP0 input must be three or more sampling clocks selected by SCS0, regardless of whether the level
is high or low. If the width is shorter than this, the pulse may not be counted.
Figure 10-10 shows the timing of the external event count by timer/event counter 1.
Table 10-4. Maximum Input Frequency and Minimum Input Pulse Width that can be Counted as Events
( ): fXX = 12.58 MHz, fCLK = 12.58 MHz
Sampling Clock Selected by SCS0
Maximum Input Frequency
Minimum Pulse Width
fCLK
fCLK/6 (2.10 MHz)
3/fCLK (0.24 µs)
fXX/32
fXX/192 (65.52 kHz)
96/fXX (7.63 µs)
fXX/64
fXX/384 (32.76 kHz)
192/fXX (15.26 µs)
fXX/128
fXX/768 (16.38 kHz)
384/fXX (30.52 µs)
Figure 10-10. Timer/Event Counter 1 External Event Count Timing (1/2)
(1) Counting one edge (maximum frequency = fCLK/6)
INTP0
ICI
3/fSMP (MIN.) 3/fSMP (MIN.) 6/fSMP (MIN.)
2-3/fSMP
TM1
Dn
Dn+1
Dn+2
Dn+3
Remarks 1. ICI: INTP0 input signal after passing through edge detection circuit
2. fSMP is selected by the sampling clock selection register (SCS0).
Preliminary User’s Manual U13987EJ1V0UM00
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