UPD784938 Datasheet, PDF (108/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 4 CLOCK GENERATOR
Figure 4-3. Standby Control Register (STBC) Format
7
6
5
4
3
STBC SELOSC 0 CK1 CK0 ×
2
1
0 Address After reset R/W
0 STP HLT 0FFC0H 30H R/W
STP HLT
Operating Mode
0
0 Normal mode
0
1 HALT mode
1
0 STOP mode
1
1 IDLE mode
CK1
0
0
1
1
(fXX = 12.58 MHz)
CK0 Internal System Clock Selection
0 fXX (12.58 MHz)
1 fXX/2 (6.29 MHz)
0 fXX/4 (3.15 MHz)
1 fXX/8 (1.57 kHz)
SELOSC
Oscillation Frequency Control
0 6.29 MHz
1 12.58 MHz
Cautions 1. Overwrite the SELOSC bit after performing the following settings.
• Stop the IEBus (Set bit 7 of the bus control register (BCR) to “0”).
• If the watch Timer is operated with the main clock selected, stop the watch timer (Set bit 3 of the
watch timer mode register (WM) to “0”).
2. If the above settings are not performed, the IEBus and watch timer may perform incorrectly.
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Preliminary User’s Manual U13987EJ1V0UM00