UPD784938 Datasheet, PDF (226/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.4 Timer Counter 0 (TM0) Operation
9.4.1 Basic operation
In the timer/event counter 0 count operation, an count-up is performed using the count clock specified by the low-order 4 bits
of prescaler mode register 0 (PRM0).
Count operation enabling/disabling is controlled by bit 3 (CE0) of timer control register 0 (TMC0). When the CE0 bit is set
(to 1) by software, the contents of TM0 are cleared to 0000H on the first count clock, and then the count-up operation is performed.
When the CE0 bit is cleared (to 0), TM0 becomes 0000H immediately, and capture operations and match signal generation
are stopped.
If the CE0 bit is set (to 1) again when it is already set (1), TM0 continues the count operation without being cleared.
If the count clock is input when TM0 is FFFFH, TM0 becomes 0000H. In this case, OVF0 bit is set (to 1) and an overflow
signal is sent to the output control circuit. OVF0 bit is cleared by software only. The count operation is continued.
When RESET is input, TM0 is cleared to 0000H, and the count operation is stopped.
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Preliminary User’s Manual U13987EJ1V0UM00