UPD784938 Datasheet, PDF (462/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 19 3-WIRE SERIAL I/O MODE
19.4.1 Basic operation timing
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit
by bit in MSB-first or LSB-first order in synchronization with the serial clock.
MSB first/LSB first switching is specified by the DIR bit of the clocked serial interface mode register (CSIM).
Transmit data is output in synchronization with the fall of SCK0, and receive data is sampled on the rise of SCK0.
An interrupt request (INTCSI) is generated on the 8th rise of SCK0.
When the internal clock is used as SCK0, SCK0 output is stopped on the 8th rise of SCK0 and SCK0 remains high until
the next data transmit or receive operation is started.
3-wire serial I/O mode timing is shown in Figure 19-4.
Figure 19-4. 3-Wire Serial I/O Mode Timing (1/2)
(a) MSB-first
SCK0^Note
SI0 (input)
SO0 (output)
1 2 34567 8
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
INTCSI
Transfer end
interrupt generation
Start of transfer synchronized with fall of SCK0
Execution of instruction that writes to SIO, etc.
Note Master CPU: Output
Slave CPU: ^Input
Cautions 1. If data is written to SIO during transfer operation after the transfer was started by writing SIO,
malfunctioning may occur. Therefore, do not rewrite SIO during the transfer operation.
2. The operation is immediately stopped even during transfer operation if the ENCSI bit is cleared
(to 0).
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Preliminary User’s Manual U13987EJ1V0UM00