UPD784938 Datasheet, PDF (502/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
20.6 Interrupt Generation Timing and Main CPU Processing
20.6.1 Master transmission
Start
Broad-
casting
<1>
M address P S address P A
Approx. 624 µ s (mode 1)
6
Control
P
A
Telegraph
length
P
A
Data 1
Approx. 390 µ s
(mode 1)
6
Data 1 P A Data 2
6
PA
6
Data n–1
5
P A Data n
<2>
PA
n = Final number of data bytes
Caution indicates that an interrupt (INTIE1) does not occur.
Initial preparation processing
Sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data.
Communication start processing
Sets the bus control register (enables communication, master request, and slave reception).
<1> Interrupt (INTIE2) occurrence
Judgment of occurrence of error
↓
Judgment of slave request
↓
Judgment of contention result
→ Error processing
→ Slave reception processing^{Note 1}
→ Remaster request processing
Interrupt (INTIE1) occurrence^{Note 2}
The transmit data of the second byte and those that follow are written to the data register (DR) by macro service.
At this time, the data transfer direction is RAM (memory) → SFR (peripheral)
<2> Interrupt (INTIE2) occurrence
Judgment of occurrence of error →
↓
Judgment of end of communication →
↓
Judgment of end of frame
→
Error processing
End of communication processing
Re-communication processing^{Note 3}
502
Preliminary User’s Manual U13987EJ1V0UM00