UPD784938 Datasheet, PDF (256/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.8.3 Pulse width measurement operation
In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input
pin (INTP3) is measured.
Both the high-level and low-level widths of pulses input to the INTP3 pin must be at least 3 system clocks (0.24 µs: fCLK
= 12.58 MHz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed.
This pulse width measurement can be performed within the range shown in Table 9-3 (fCLK = 12.58 MHz).
As shown in Figure 9-37, the timer counter 0 (TM0) value being counted is fetched into the capture register (CR02) in
synchronization with a valid edge (specified as both rising and falling edges) in the INTP3 pin input, and held there. The pulse
width is obtained from the product of the difference between the TM0 count value (Dn) fetched into and held in the CR02 on
detection of the nth valid edge and the count value (Dn-1) fetched and held on detection of valid edge n-1, and the number of
count clocks (x/fXX; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024).
The control register settings are shown in Figure 9-38, and the setting procedure in Figure 9-39.
Figure 9-37. Pulse Width Measurement Timing
FFFFH
FFFFH
TM0
count value
D1
D3
D0
0H
Capture
Count start
Capture
D2
Capture
Capture
INTP3
external input signal
INTP3
interrupt request
(D1-D0) × 8/fXX
(10000H-D1+
D2) × 8/fXX
(D3-D2) × 8/fXX
Capture register
(CR02)
D0
D1
D2
D3
OVF0
Remark Dn: TM0 count value (n = 0, 1, 2, ...)
x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024
↑
Cleared by software
256
Preliminary User’s Manual U13987EJ1V0UM00