UPD784938 Datasheet, PDF (559/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
Figure 23-15. Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting
Main routine
IMC ← 80H
EI
Interrupt request a
(level 3)
Interrupt
request b
(level 3)
a servicing
EI
b servicing
The PRSL bit of the IMC is set to 1, and
nesting between level 3 interrupts is
disabled.
Even though interrupts are enabled, interrupt
request b is held pending since it has the
same priority as interrupt request a.
Main routine
IMC ← 00H
EI
c servicing
The PRSL bit of the IMC is set to 0, so that a
level 3 interrupt is acknowledged even during
level 3 interrupt servicing (nesting is
possible).
Interrupt request c
(level 3)
EI
Interrupt
request d
(level 3)
d servicing
Since level 3 interrupt request c is being
serviced in the interrupt enabled state and
PRSL = 0, interrupt request d, which is also
level 3, is acknowledged.
Main routine
IMC ← 00H
Interrupt request e ^Note1
(level 3)
Interrupt request f ^Note2
(level 3)
EI
f servicing
EI
e servicing
As interrupt requests e and f are the
same level, the one with the higher default
priority, f, is acknowledged first.
When the interrupt enabled state is set
during servicing of interrupt request f,
pending interrupt request e is acknowledged
since PRSL = 0.
Notes 1. Low default priority
2. High default priority
Remarks 1. “a” to “f” in the figure are arbitrary names used to differentiate between the interrupt requests and macro
service requests.
2. High or low in default priorities in the figure indicate the relative priority levels of the two interrupt requests.
Preliminary User’s Manual U13987EJ1V0UM00
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