UPD784938 Datasheet, PDF (73/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 3 CPU ARCHITECTURE
3.2 Internal ROM Area
The µPD784938 Subseries products shown below incorporate ROM which is used to store programs, table data, etc.
If the internal ROM area and internal data area overlap when the LOCATION 0 instruction is executed, the internal data area
is accessed, and the overlapping part of the internal ROM area cannot be accessed.
Part Number
µPD784935
µPD784936
µPD784937
µPD784938
µPD78F4938
Internal ROM
Address Space
LOCATION 0 Instruction LOCATION 0FH Instruction
96 Kbytes × 8 bits
00000H to 0EAFFH
10000H to 17FFFH
00000H to 17FFFH
128 Kbytes × 8 bits 00000H to 0E4FFH
10000H to 1FFFFH
00000H to 1FFFFH
192 Kbytes × 8 bits 00000H to 0DEFFH
10000H to 2FFFFH
00000H to 2FFFFH
256 Kbytes × 8 bits 00000H to 0D5FFH
10000H to 3FFFFH
00000H to 3FFFFH
The internal ROM can be accessed at high speed. Normally, fetches are performed at the same speed as external ROM,
but if the IFCH bit of the memory expansion mode register (MM) is set (to 1), the high-speed fetch function is used and internal
ROM fetches are performed at high speed (2-byte fetch performed in 2 system clocks).
When the instruction execution cycle equal to an external ROM fetch is selected, wait insertion is performed by the wait
function, but when high-speed fetches are used, wait insertion is not performed for internal ROM.
RESET input sets the instruction execution cycle equal to the external ROM fetch cycle.
Preliminary User’s Manual U13987EJ1V0UM00
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