UPD784938 Datasheet, PDF (105/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 4 CLOCK GENERATOR
4.1 Configuration and Function
The clock generator generates and controls the internal clock and internal system clock supplied to the CPU and on-chip
hardware. The clock generator block diagram is shown in Figure 4-1.
Figure 4-1. Clock Generator Block Diagram
Internal bus
EXTC
OSTS
OSTS2 OSTS1 OSTS0 RESET SELOSC
CK1 CK0
STBC
STP HLT
RESET
X1
Clock oscillator
fXX
X2
Clock supplied to watch
timer when the main clock
selected (WM6 = 0)
fXX
fXX/2
fXX/4
fXX/8
1/2 divider
SELOSC = 1
fCLK _{Internal system clock}
(CPU, watchdog timer, noise
elimination circuit, A/D, PWM,
interrupts, local bus interface)
fXX _{Internal clock}
(UART/IOE, CSI, noise elimination
circuit, timer/counters, oscillation
stabilization timer)
IEBus
Remark fXX: Crystal/ceramic oscillation frequency or internal clock frequency
fCLK: Internal system clock frequency
The clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the X1 and X2 pins. When
standby mode (STOP) is set, oscillation stops (see CHAPTER 25 STANDBY FUNCTION).
It is also possible to input an external clock. In this case, the clock signal is input to the X1 pin, and the inverse phase signal
to the X2 pin.
The frequency divider generates an internal system clock by 1/1, 1/2, 1/4, or 1/8 scaling of the clock oscillator output (fXX)
according to the setting of the standby control register (STBC).
Preliminary User’s Manual U13987EJ1V0UM00
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