UPD784938 Datasheet, PDF (646/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 25 STANDBY FUNCTION
25.4 STOP Mode
25.4.1 STOP mode setting and operating status
The STOP mode is selected by setting (to 1) the STP bit of the standby control register (STBC) register.
The only writes that can be performed on STBC are 8-bit data writes by means of a dedicated instruction. STOP mode
setting is therefore performed by means of the “MOV STBC, #byte” instruction.
Caution If the STOP mode is set when the condition to release the HALT mode is satisfied (refer to 25.3.2 HALT
mode release), the STOP mode is not set, but the next instruction is executed or execution branches
to a vectored interrupt service program. To accurately set the STOP mode, clear the interrupt request
before setting the STOP mode.
Table 25-4. Operating Status in STOP Mode
Clock oscillator
Internal system clock
CPU
I/O lines
Peripheral functions
Internal RAM
Bus lines
RD, WR output
ASTB output
REFRQ output
HLDRQ input
HLDAK output
AD0 to AD7
A8 to A19
Oscillation stopped
Stopped
Operation stopped
Retain state prior to STOP mode setting
All operation stopped^Note
Retained
High-impedance
High-impedance
High-impedance
High-impedance
Retained
High-impedance
Low level
Note A/D converter operation is stopped, but if the CS bit of the A/D converter mode register (ADM) is set (to 1), the
current consumption does not decrease.
Cautions 1. If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS)
register is cleared (to 0), the X1 pin is shorted internally to VSS (GND potential) to suppress clock
generator leakage. Therefore, when the STOP mode is used in a system that uses an external clock,
the EXTC bit of OSTS must be set (to 1). If STOP mode setting is performed in a system to which
an external clock is input when the EXTC bit of OSTS is cleared (to 0), the µPD784938 may suffer
damage or reduced reliability.
When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the
clock input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).
2. The CS bit of the A/D converter mode (ADM) register should be cleared (to 0).
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Preliminary User’s Manual U13987EJ1V0UM00