UPD784938 Datasheet, PDF (286/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 10 TIMER/EVENT COUNTER 1
Figure 10-10. Timer/Event Counter 1 External Event Count Timing (2/2)
(2) Counting both edges (maximum frequency = fCLK/6)
INTP0
3/fSMP (MIN.) 3/fSMP (MIN.)
6/fSMP (MIN.)
2-3/fSMP
ICI
TM1
Dn
Dn+1
Dn+2
Dn+3
Dn+4
Dn+5
Remarks 1. ICI: INTP0 input signal after passing through edge detection circuit
2. fSMP is selected by the sampling clock selection register (SCS0).
The TM1 count operation is controlled by the CE1 bit of the timer control register 1 (TMC1) in the same way as with the basic
operation.
When the CE1 bit is set (to 1) by software, the contents of TM1 are set to 0H and the count-up operation is started on the
initial count clock.
When the CE1 bit is cleared (to 0) by software during a TM1 count operation, the contents of TM1 are set to 0H immediately
and the stopped state is entered. The TM1 count operation is not affected if the CE1 bit is set (to 1) by software again when
it is already set (to 1).
Caution When timer/event counter 1 is used as an external event counter, it is not possible to distinguish between
the case where there is no valid edge input at all and the case where there is a single valid edge input using
the timer counter 1 (TM1) alone (see Figure 10-11), since the contents of TM1 are 0 in both cases. If it is
necessary to make this distinction, the INTP0 interrupt request flag should be used. An example is shown
in Figure 10-12.
Figure 10-11. Example of the Case where the External Event Counter does Not Distinguish between One
Valid Edge Input and No Valid Edge Input
INTP0
TM1 0
0
No distinction made
Count start
1
2
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Preliminary User’s Manual U13987EJ1V0UM00