UPD784938 Datasheet, PDF (654/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 25 STANDBY FUNCTION
(2) Is the input pin level appropriate?
The voltage level input to each pin should be in the range between VSS potential and VDD potential. If a voltage outside
this range is applied, the current consumption will increase and the reliability of the µPD784938 may be adversely
affected.
Also ensure that an intermediate potential is not applied.
(3) Are pull-up resistors necessary?
An unnecessary pull-up resistor will increase the current consumption and cause a latchup of other devices. A mode
should be specified in which pull-up resistors are used only for parts that require them.
If there is a mixture of parts that do and do not require pull-up resistors, for parts that do, you should connect a pull-
up resistor externally and specify a mode in which the on-chip pull-up resistor is not used.
(4) Is processing of the address bus, address/data bus, etc., appropriate?
In STOP mode and IDLE mode, the address bus, address/data bus, RD and WR pins become high-impedance.
Normally, these pins are pulled high with a pull-up resistor. If this pull-up resistor is connected to the backed-up power
supply, then if the input impedance of circuitry connected to the non-backed-up power supply is low, a current will flow
through the pull-up resistor, and the current consumption will increase. Therefore, the pull-up resistor should be
connected to the non-backed-up power supply side as shown in Figure 25-7.
Also, in STOP mode and IDLE mode the ASTB pin also becomes high impedance, and the REFRQ/HLDAK pin adopts
a fixed level. Countermeasures should be taken with reference to the points noted in (to 1).
Figure 25-7. Example of Address/Data Bus Processing
Backed-up power supply
Non-backed-up power supply
VDD
µ PD784938
ADn
(n = 0 to 7)
VSS
VDD
CMOS IC, etc.
IN/OUT
VSS
The voltage level input to the WAIT/HLDRQ pin should be in the range between VSS potential and VDD potential. If
a voltage outside this range is applied, the current consumption will increase and the reliability of the µPD784938 may
be adversely affected.
(5) A/D converter
The current flowing to the AVDD, AVREF1 pins can be reduced by clearing (0) the CS bit (bit 7) of the A/D converter mode
register (ADM). The current can be further reduced, if required, by cutting the current supply to the AVDD, AVREF1 pins
with external circuitry.
Make sure that the AVDD pin is not at the same potential as the VDD pin. Unless power is supplied to the AVDD pin in
the STOP mode, not only does the current consumption increase, but the reliability is also affected.
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Preliminary User’s Manual U13987EJ1V0UM00