UPD784938 Datasheet, PDF (530/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
23.3 Interrupt Service Control Registers
µPD784938 interrupt service is controlled for each interrupt request by various control registers that perform interrupt
service specification. The interrupt control registers are listed in Table 23-3.
Table 23-3. Control Registers
Register Name
Interrupt control registers
Interrupt mask registers
In-service priority register
Interrupt mode control register
Watchdog timer mode register
Program status word
Symbol
PIC0
PIC1
PIC2
PIC3
CIC00
CIC01
CIC10
CIC11
CIC20
CIC21
CIC30
PIC4
PIC5
ADIC
SERIC
SRIC
CSIIC1
STIC
CSIIC
SERIC2
SRIC2
CSIIC2
STIC2
IEIC1
IEIC2
WIC
CSIIC3
MK0
MK1
ISPR
IMC
WDM
PSW
Function
Registers that perform each interrupt request generation recording, mask
control, vectored interrupt service or macro service specification, context
switching function enabling/disabling, and priority specification.
Maskable interrupt request mask control
Linked to mask control flags in interrupt control registers
Word accesses or byte accesses possible
Records priority of interrupt request currently being acknowledged
Controls nesting of maskable interrupts for which lowest priority level
(level 3) is specified
Specifies priority of interrupts due to NMI pin input and interrupts due to
watchdog timer overflow
Specifies enabling/disabling of maskable interrupt acknowledgment
An interrupt control register is allocated to each interrupt source. The flags of each register perform control of the contents
corresponding to the relevant bit position in the register. The interrupt control register flag names corresponding to each
interrupt request signal are shown in Table 23-4.
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Preliminary User’s Manual U13987EJ1V0UM00