UPD784938 Datasheet, PDF (230/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.5 External Event Counter Function
The timer/event counter 0 can count clock pulses input from the external interrupt request input pin (INTP3).
No special selection method is needed for the external event counter operation mode. When the timer counter 0 (TM0) count
clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 0 (PRM0), TM0 operates
as an external event counter.
The maximum frequency of external clock pulses that can be counted by TM0 as the external event counter is 2.10 MHz (fCLK
= 12.58 MHz) irrespective of whether only one edge or both edges are counted on INTP3 input.
The pulse width of the INTP3 input must be at least 3 system clocks (0.24 µs: fCLK = 12.58 MHz) for both the high level and
low level. If the pulse width is shorter than this, the pulse may not be counted.
The timer/event counter 0 external event counter timing is shown in Figure 9-10.
Figure 9-10. Timer/Event Counter 0 External Event Count Timing
(1) Counting one edge (maximum frequency = fCLK/6)
INTP3
3/fCLK (MIN.) 3/fCLK (MIN.) 6/fCLK (MIN.)
2-3/fCLK
ICI
TM0
Dn
Dn+1
Dn+2
Dn+3
Remark ICI: INTP3 input signal after passing through edge detection circuit
(2) Counting both edges (maximum frequency = fCLK/6)
INTP3
3/fCLK (MIN.) 3/fCLK (MIN.)
6/fCLK (MIN.)
2-3/fCLK
ICI
TM0
Dn
Dn+1
Dn+2
Dn+3
Dn+4
Remark ICI: INTP3 input signal after passing through edge detection circuit
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Preliminary User’s Manual U13987EJ1V0UM00
Dn+5