UPD784938 Datasheet, PDF (615/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
24.2 Wait Function
When a low-speed memory or I/O is connected externally to the µPD784938, waits can be inserted in the external memory
access cycle.
There are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing
the access time.
24.2.1 Wait function control registers
(1) Memory expansion mode register (MM)
The IFCH bit of MM performs wait control setting for internal ROM accesses, and the AW bit performs address wait
setting.
MM can be read or written to with an 8-bit manipulation instruction. The MM format is shown in Figure 24-8.
When RESET is input, MM is set to 20H, the same cycle as for external memory is used for internal ROM accesses,
and the address wait function is validated.
Figure 24-8. Memory Expansion Mode Register (MM) Format
7
6
5
4
3
2
1
0 Address After reset R/W
MM IFCH 0 AW 0 MM3 MM2 MM1 MM0 0FFC4H 20H R/W
Memory expansion mode settings (see 24.1
Memory Extension Function)
AW
Address Wait Specification
0 Disabled
1 Enabled
IFCH
Internal ROM Fetches
0 Fetch performed at same speed as
external memory
All wait control settings valid
1 High-speed fetches performed
Wait control specification invalid
(2) Programmable wait control registers (PWC1/PWC2)
PWC1 and PWC2 specify the number of waits.
PWC1 is an 8-bit register that divides the space from 0 to FFFFH into four, and specifies wait control for each of these
four spaces. PWC2 is a 16-bit register that divides the space from 10000H to FFFFH into four, and specifies wait control
for each of these four spaces.
PWC1 can be read or written to with an 8-bit manipulation instruction, and PWC2 with a 16-bit manipulation instruction.
The PWC1 and PWC2 formats are shown in Figure 24-9.
The high-order 8 bits of PWC2 are fixed at AAH, and therefore ensure that the high-order 8 bits are set to AAH.
When RESET is input, PWC1 is set to AAH, and PWC2 to AAAAH, and 2-wait insertion is performed on the entire space.
Preliminary User’s Manual U13987EJ1V0UM00
615