UPD784938 Datasheet, PDF (561/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 23 INTERRUPT FUNCTIONS
Table 23-6. Interrupts for which Macro Service can be Used
Default
Priority
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Interrupt Request Generation Source
INTP0 (pin input edge detection)
INTP1 (pin input edge detection)
INTP2 (pin input edge detection)
INTP3 (pin input edge detection)
INTC00 (TM0-CR00 match signal generation)
INTC01 (TM0-CR01 match signal generation)
INTC10 (TM1-CR10 or TM1W-CR10W match signal generation)
INTC11 (TM1-CR11 or TM1W-CR11W match signal generation)
INTC20 (TM2-CR20 or TM2W-CR20W match signal generation)
INTC21 (TM2-CR21 or TM2W-CR21W match signal generation)
INTC30 (TM3-CR30 or TM3W-CR30W match signal generation)
INTP4 (pin input edge detection)
INTP5 (pin input edge detection)
INTAD (A/D conversion end)
INTSR (asynchronous serial interface reception end)
INTCSI1 (clocked serial interface transfer end)
INTST (asynchronous serial interface transmission end)
16
INTCSI (clocked serial interface transfer end)
17
INTSR2 (asynchronous serial interface 2 reception end)
INTCSI2 (clocked serial interface 2 transfer end)
18
INTST2 (asynchronous serial interface 2 transmission end)
19
INTIE1 (IEBus data access request)
20
INTIE2 (IEBus communication error and communication end)
21
INTW (watch timer output)
22
INTCSI3 (clocked serial interface 3 transfer end)
Generating Unit
Macro Service Control
Word Address
Edge detection
0FE06H
0FE08H
0FE0AH
0FE0CH
Timer/event counter 0
0FE0EH
0FE10H
Timer/event counter 1
0FE12H
0FE14H
Timer/event counter 2
0FE16H
0FE18H
Timer 3
0FE1AH
Edge detection
0FE1CH
0FE1EH
A/D converter
0FE20H
Asynchronous
serial interface/
clocked serial
interface 1
0FE24H
0FE26H
Clocked serial
interface
Asynchronous
serial interface 2/
clocked serial
interface 2
0FE28H
0FE2CH
0FE2EH
IEBus controller
Watch timer
Clocked serial
interface 3
0FE32H
0FE34H
0FE36H
0FE38H
Remarks 1. The default priority is a fixed number. This indicates the order of priority when macro service requests
are generated simultaneously,
2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used
simultaneously). Therefore, although the same hardware is used for the interrupts, two names are
provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2.
Preliminary User’s Manual U13987EJ1V0UM00
561