UPD784938 Datasheet, PDF (655/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 25 STANDBY FUNCTION
25.7 Cautions
(1) If HALT/STOP/IDLE mode (standby mode hereafter) setting is performed when a condition that release HALT mode
(refer to 25.3.2 HALT mode release) is satisfied, standby mode is not entered, and execution of the next instruction,
or a branch to a vectored interrupt service program, is performed. To ensure that a definite standby mode setting is
made, interrupt requests should be cleared, etc. before entering standby mode.
(2) When crystal/ceramic oscillation is used, the EXTC bit must be cleared (to 0) before use. If the EXTC bit is set (to
1), oscillation will stop.
(3) If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS) register is cleared
(to 0), the X1 pin is shorted internally to VSS (GND potential) to suppress clock generator leakage. Therefore, when
the STOP mode is used in a system that uses an external clock, the EXTC bit of OSTS must be set (to 1). If STOP
mode setting is performed in a system to which an external clock is input when the EXTC bit of the OSTS is cleared
(to 0), the µPD784938 may suffer damage or reduced reliability.
When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the X1
pin, to the X2 pin (refer to 4.3.1 Clock oscillator).
(4) In STOP mode and IDLE mode, the CS bit of the A/D converter mode ADM register should be cleared (to 0).
Preliminary User’s Manual U13987EJ1V0UM00
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