UPD784938 Datasheet, PDF (228/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
9.4.2 Clear operation
(1) Clear operation after a match with the compare register
The timer counter 0 (TM0) can be cleared automatically after a match with the compare register (CR01). When a clearance
source arises, TM0 is cleared to 0000H on the next count clock. Therefore, even if a clearance source arises, the value
at the point at which the clearance source arose is retained until the next count clock arrives.
Figure 9-8. TM0 Clearance by Match with Compare Register (CR01)
Count clock
TM0
n-1
n
0
1
Compare register
(CR01)
n
TM0 and CR01 match Cleared here
(2) Clear operation by the CE0 bit of the timer control register 0 (TMC0)
The timer counter 0 (TM0) is also cleared when the CE0 bit of TMC0 is cleared (to 0) by software. The clear operation is
performed immediately after clearance (to 0) of the CE0 bit.
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Preliminary User’s Manual U13987EJ1V0UM00