UPD784938 Datasheet, PDF (514/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 21 CLOCK OUTPUT FUNCTION
21.3 Operation
21.3.1 Clock output
A signal with the clock output frequency selected by bits FS0 to FS2 is selected by selector 1 and output.
The output signal has the same level as the LV bit when the CLE bit is cleared (to 0), and is output from the clock signal
immediately after the CLE bit is set (to 1).
When the CLE bit is cleared (to 0), the contents of the LV bit are output in synchronization with the clock signal, and
further output operations are stopped.
Figure 21-3. Clock Output Operation Timing
(a) LV = 0
fCLK/n
(n = 1, 2, 4, 8, 16)
CLE
CLOCKOUT
(b) LV = 1
fCLK/n
(n = 1, 2, 4, 8, 16)
CLE
CLOCKOUT
Setting of bits FS0 to FS2 and the LV bit should only be performed when CLE = 0 (bits FS0 to FS2 and the LV bit should
not be changed within the same instruction that changes the CLE bit contents).
<Operation Example>
MOV CLOM, #82H; CLOCKOUT pin: high level, clock output: fCLK/4
SET1 CLE;
Starts clock output
CLR1 CLE;
Stops clock output, CLOCKOUT pin: high level
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Preliminary User’s Manual U13987EJ1V0UM00