82583V Datasheet, PDF (99/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.2.3.1.2 MAC Speed Resolution
For proper link operation, both the MAC and PHY must be configured for the same
speed of link operation. The speed of the link can be determined and set by several
methods with the 82583V. These include:
• Software-forced configuration of the MAC speed setting based on PHY indications,
which can be determined as follows:
— Software reads of PHY registers directly to determine the PHY's auto-negotiated
speed
— Software reads the PHY's internal PHY-to-MAC speed indication (SPD_IND)
using the MAC STATUS.SPEED register
— Software signals the MAC to attempt to auto-detect the PHY speed from the
PHY-to-MAC RX_CLK, then programs the MAC speed accordingly
• The MAC automatically detecting and setting the link speed of the MAC based on
PHY indications by:
— Using the PHY's internal PHY-to-MAC speed indication (SPD_IND), setting the
MAC speed automatically
— Attempting to auto-detect the PHY speed from the PHY-to-MAC RX_CLK and
setting the MAC speed automatically
Aspects of these methods are discussed in the sections that follow.
6.2.3.1.2.1 Forcing MAC Speed
There might be circumstances when the software device driver must forcibly set the
link speed of the MAC. This can occur when the link is manually configured. To force the
MAC speed, the software device driver must set the CTRL.FRCSPD (force-speed) bit to
1b and then write the speed bits in the Device Control register (CTRL.SPEED) to the
desired speed setting. See section 9.2.2.1 for details.
Note:
Forcing the MAC speed using CTRL.FRCSPD overrides all other mechanisms for
configuring the MAC speed and can yield non-functional links if the MAC and PHY are
not operating at the same speed/configuration.
When forcing the 82583V to a specific speed configuration, the software device driver
must also ensure the PHY is configured to a speed setting consistent with MAC speed
settings. This implies that software must access the PHY registers to either force the
PHY speed or to read the PHY status register bits that indicate link speed of the PHY.
Note:
Forcing speed settings by CTRL.SPEED can also be accomplished by setting the
CTRL_EXT.SPD_BYPS bit. This bit bypasses the MAC's internal clock switching logic and
enables the software device driver complete control of when the speed setting takes
place. The CTRL.FRCSPD bit uses the MAC's internal clock switching logic, which does
delay the affect of the speed change.
6.2.3.1.2.2 Using PHY Direct Link-Speed Indication
The 82583V PHY provides a direct internal indication of its speed to the MAC
(SPD_IND). The most direct method for determining the PHY link speed and either
manually or automatically configuring the MAC speed is based on these direct speed
indications.
For MAC speed to be set/determined from these direct internal indications from the
PHY, the MAC must be configured such that CTRL.ASDE and CTRL.FRCSPD are both 0b
(both auto-speed detection and forced-speed override are disabled). As a result, the
MAC speed is reconfigured automatically each time the PHY indicates a new link-up
event to the MAC.
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