82583V Datasheet, PDF (177/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Power Management and Delivery—82583V GbE Controller
8.4.4.4
Note:
Device Disable
For a LOM design, it might be desirable for the system to provide BIOS-setup capability
for selectively enabling or disabling LOM devices. This might allow the designers more
control over system resource-management, avoid conflicts with add-in NIC solutions,
etc. The 82583V provides support for selectively enabling or disabling it.
• Device Disable - the device is in a global power down state.
Device disable is initiated by asserting the asynchronous DEV_OFF_N pin. The
DEV_OFF_N pin has an internal pull-up resistor, so that it can be left not connected to
enable device operation.
While in device disable mode, the PCIe link is in L3 state. The PHY is in power-down
mode. All internal clocks are gated. Output buffers are tri-stated.
Asserting or de-asserting PCIe PE_RST_N does not have any effect while the device is
in device disable mode (for example, the device stays in the respective mode as long as
DEV_OFF_N is asserted). However, the device might momentarily exit the device
disable mode from the time PCIe PE_RST_N is de-asserted again and until the NVM is
read.
Note to system designers: The DEV_OFF_N pin should maintain its state during system
reset and system sleep states. It should also insure the proper default value on system
power up. For example, a system designer could use a GPIO pin that defaults to 1b
(enable) and is on system suspend power (for example, it maintains state in S0-S5
ACPI states).
8.4.4.5
Link-Disconnect
In any of D0u, D0a, D3, or Dr states, the 82583V enters a link-disconnect state if it
detects a link-disconnect condition on the Ethernet link. Note that the link-disconnect
state is invisible to software (other than the Link Energy Detect bit state). In particular,
while in D0 state, software might be able to access any of the device registers as in a
link-connect state.
During link disconnect mode, the CCM PLL might be shut down. See Section 8.4.4.5.
8.4.5
Timing of Power-State Transitions
The following sections give detailed timing for the state transitions. In the diagrams the
dotted connecting lines represent the 82583V requirements, while the solid connecting
lines represent the 82583V guarantees.
The timing diagrams are not to scale. The clocks edges are shown to indicate running
clocks only, they are not used to indicate the actual number of cycles for any operation.
8.4.5.1
Transition From D0a to D3 and Back Without PE_RST_N
Figure 41 shows the 82583V’s reaction to a D3 transition.
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