82583V Datasheet, PDF (175/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Power Management and Delivery—82583V GbE Controller
8.4.4.2.3
Entry to D3 State
Transition to the D3 state is through a configuration write to the Power State field of the
PCI-PM registers.
Prior to transition from D0 to the D3 state, the software device driver disables
scheduling of further tasks to the 82583V, as follows:
• It masks all interrupts
• It does not write to the Transmit Descriptor Tail (TDT) register
• It does not write to the Receive Descriptor Tail (RDT) register
• Operates the master disable algorithm as defined in Section 6.1.3.10.
If wake-up capability is needed, the software device driver should set up the
appropriate wake-up registers and the system should write a 1b to the PME_En bit in
the PMCSR or to the AUX Power PM Enable bit of the PCIe Device Control register prior
to the transition to D3.
As a response to being programmed into the D3 state, the 82583V brings its PCIe link
into the L1 link state. As part of the transition into L1 state, the 82583V suspends
scheduling of new Transaction Layer Protocols (TLPs) and waits for the completion of all
previous TLPs it has sent. The 82583V clears the Memory Access Enable and I/O Access
Enable bits of the PCI Command register, which disables memory access decode. Any
receive packets that have not been transferred into system memory are kept in the
device (and discarded later on D3 exit). Any transmit packets that were not sent, can
still be transmitted (assuming the Ethernet link is up).
To reduce power consumption, if APM wake and PCI-PM PME are enabled, the PHY auto-
negotiates to a lower link speed on D3 entry (see Section 8.4.4.2.3).
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